1. Field of the Invention
The invention generally relates to USB (Universal Serial Bus) OTG (On-The-Go) controller devices and more generally to integrated circuit chips having circuitry for controlling data transfer to and/or from at least one peripheral device which selectively has device or host functionality and which is connected to a serial bus.
2. Description of the Related Art
The Universal Serial Bus was originally developed in 1995 to define an external expansion bus which facilitates the connection of additional peripherals to a computer system. The USB technique is implemented by PC (Personal Computer) host controller hardware and software and by peripheral friendly master-slave protocols and achieves robust connections and cable assemblies. USB systems are extendable through multi-port hubs.
In USB systems, the role of the system software is to provide a uniform view of the input/output architecture for all applications software by hiding hardware implementation details. In particular, it manages the dynamic attach and detach of peripherals and communicates with the peripheral to discover its identity. During run time, the host initiates transactions to specific peripherals, and each peripheral accepts its transactions and response accordingly.
Hubs are incorporated to the system to provide additional connectivity for USB peripherals, and to provide managed power to attached devices. The peripherals are slaves that must react to request transactions sent from the host. Such request transactions include requests for detailed information about the device and its configuration.
While these functions and protocols were already implemented in the USB 1.1 specification, this technique was still improved in order to provide a higher performance interface. FIG. 1 illustrates an example USB 2.0 system that comprises a host controller 100, a number of USB devices 115, 120, 125, 130, and two hubs 105, 110. In the system of FIG. 1, the hubs 105, 110 are introduced for increasing connectivity, but in other USB systems, the USB devices can be connected directly to the host controller 100.
As mentioned above, USB 2.0 provides a higher performance interface, and the speed improvement may be up to a factor of 40. Moreover, as apparent from FIG. 1, USB 2.0 is backwards compatible with USB 1.1 because it allows for connecting USB 1.1 devices 120, 125, 130 to be driven by the same host controller 100. There may even be used USB 1.1 hubs 110.
As can be seen from FIG. 1, a USB 1.1 device 120 can be connected directly to a USB 2.0 hub 105. Moreover, it can also be connected directly to the host controller 100. This is made possible by the capability of USB 2.0 host controllers and hubs to negotiate higher as well as lower transmission speeds on a device-by-device basis.
Turning now to FIG. 2, the system software and hardware of a USB 2.0 system is illustrated. The system components can be organized hierarchically by defining several layers as shown in the figure.
In the uppermost layer, the client driver software 200 executes on the host PC and corresponds to a particular USB device 230. The client software is typically part of the operating system or provided with the device.
The USB driver 205 is a system software bus driver that abstracts the details of the particular host controller driver 210, 220 for a particular operating system. The host controller drivers 210, 220 provide a software layer between a specific hardware 215, 225, 230 and the USB driver 205 for providing a driver-hardware interface.
While the layers discussed so far are software implemented, the uppermost hardware component layer includes the host controllers 215, 225. These controllers are connected to the USB device 230 that performs the end user function.
As apparent from the figure, there is one host controller 225 which is an enhanced host controller (EHC) for the high speed USB 2.0 functionality. This host controller operates in compliance with the EHCI (Enhanced Host Controller Interface) specification for USB 2.0. On the software side, host controller 225 has a specific host controller driver (EHCD) 220 associated.
Further, there are host controllers 215 for full and low speed operations. The UHCI (Universal Host Controller Interface) or OHCI (Open Host Controller Interface) are the two industry standards applied in the universal or open host controllers (UHC/OHC) 215 for providing USB 1.1 host controller interfaces. The host controllers 215 have assigned universal/open host controller drivers (UHCD/OHCD) 210 in the lowest software level.
Thus, the USB 2.0 compliant host controller system comprises driver software and host controller hardware which must be compliant to the EHCI specification. While this specification defines the register-level interface and associated memory-resident data structures, it does not define nor describe the hardware architecture required to build a compliant host controller.
Referring now to FIG. 3, the hardware components of a common motherboard layout are depicted. The basic elements found on a motherboard may include the CPU (Central Processing Unit) 300, a northbridge 305, a southbridge 310, and system memory 315. The northbridge 305 is usually a single chip in a core-logic chipset that connects the processor 300 to the system memory 315 and the AGP (Accelerated Graphic Port) and PCI (Peripheral Component Interface) buses. The PCI bus is commonly used in personal computers for providing a data path between the processor and peripheral devices like video cards, sound cards, network interface cards and modems. The AGP bus is a high-speed graphic expansion bus that directly connects the display adapter and system memory 315. AGP operates independently of the PCI bus. It is to be noted that other motherboard layouts exist that have no northbridge in it, or that have a northbridge without AGP or PCI options.
The southbridge 310 is usually the chip in a system core-logic chipset that controls the IDE (Integrated Drive Electronics) or EIDE (Enhanced IDE) bus, the USB bus, that provides plug-n-play support, controls a PCI-ISA (Industry Standard Architecture) bridge, manages the keyboard/mouse controller, provides power management features, and controls other peripherals.
USB functionality is often implemented in a southbridge device or in other companion chips that may be part of a personal computer's chipset. As described above, this functionality provides a popular interface for exchanging data between the computer that has built in the southbridge or companion chip, and peripherals.
In order to allow low-power devices to have limited host capabilities, the “On-The-Go Supplement to the USB 2.0 Specification” has been drafted. The supplement defines two protocols: SRP (Session Request Protocol), which lets a peripheral device ask the host to turn on the USB power, and HNP (Host Negotiation Protocol), which lets a peripheral device become the USB host. Thus, the supplement to the USB 2.0 specification allows a portable device to take on the role of a limited USB host without the burden of supporting all of the USB functions of a personal computer.
Besides others, the OTG supplement specifies dual-role devices that may be operated in full speed (and optionally in high speed) as peripheral, and further in full speed (and optionally in low and high speed) as host. Further, an A-device is specified to be a host at the start of a session. Under certain conditions, the A-device will relinquish the role of host to a dual-role B-device. A B-device is a peripheral at the start of a session. If the device is dual-role, it may be granted the role of host from the A-device.
One way to create a USB 2.0 OTG dual-role device controller has been described in the German patent application number 10 2004 057 756.0 entitled “USB On-The-Go Controller”, filed Nov. 30, 2004. A similar arrangement is shown in FIG. 4.
The USB controller device 400 of FIG. 4 has host control units 225, 215, a device control unit 410, a bridge 405, and an OTG controller 415. The host control units form an EHC/UHC/OHC combination and the OTG controller 415 implements OTG functionality to the USB controller device 400. Further, there is a port router 420 for controlling access of the host control units 225, 215 and the device control unit 410 to the shared physical port.
This bundle approach has specific advantages since it may use well-defined, partially even silicon-proven blocks and it allows the use of existing driver software with just some additional OTG controller driver modifications. Further, the arrangement of FIG. 4 may be potentially implemented in a quite short development time.
However, this approach may lead to a non-integrated, non-coherent cluster of designs with different bus interfaces for each part, and may further have a higher degree of redundancy resulting in a considerable size penalty. For instance, the total size of the USB controller device shown in FIG. 4 may be estimated to be in the range of 330 to 390 kgates. Further, as far as the approach of FIG. 4 uses existing designs which have not been optimized for low power consumption, this device may require further circuit development to reduce the power consumption. Moreover, at least the conventional EHCI software interface may create a significant amount of redundant traffic on the system bus, and the bundle approach of FIG. 4 may further lead to long combinational paths in certain situations.